for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. _______________________________________________________________ maxim integrated products 1 general description the DS4422 and ds4424 contain two or four i 2 c pro- grammable current dacs that are each capable of sinking and sourcing current up to 200?. each dac output has 127 sink and 127 source settings that are programmed using the i 2 c interface. the current dac outputs power up in a high-impedance state. applications power-supply adjustment power-supply margining adjustable current sink or source features ? two (DS4422) or four (ds4424) current dacs ? full-scale current 50 a to 200 a ? full-scale range for each dac determined by external resistors ? 127 settings each for sink and source modes ? i 2 c-compatible serial interface ? two address pins allow four devices on same i 2 c bus ? low cost ? small package (14-pin, 3mm x 3mm tdfn) ? -40? to +85? temperature range ? 2.7v to 5.5v operating range DS4422/ds4424 two-/four-channel, i 2 c, 7-bit sink/source current dac dc-dc converter fb out sda scl a0 a1 out0 out1 gnd r fs0 r fs1 r pu r pu v cc v cc v out0 fs0 fs1 r 0b r 0a dc-dc converter fb out v out1 r 1b r 1a DS4422/ ds4424 typical operating circuit ordering information rev 0; 3/08 + denotes a lead-free package. t&r = tape and reel. part outputs temp range pin- package DS4422 n+ 2 -40c to +85c 14 tdfn DS4422n+t&r 2 -40c to +85c 14 tdfn ds4424 n+ 4 -40c to +85c 14 tdfn ds4424n+t&r 4 -40c to +85c 14 tdfn pin configuration appears at end of data sheet.
DS4422/ds4424 two-/four-channel, i 2 c, 7-bit sink/source current dac 2 _______________________________________________________________________________________ absolute maximum ratings recommended operating conditions (t a = -40? to +85?.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. voltage range on v cc , sda, and scl relative to ground.............................................-0.5v to +6.0v voltage range on a0, a1, fs0, fs1, fs2, fs3, out0, out1, out2, and out3 relative to ground ................-0.5v to (v cc + 0.5v) (not to exceed 6.0v.) operating temperature range ...........................-40? to +85? storage temperature range .............................-55? to +125? soldering temperature ...............................refer to the ipc/jedec j-std-020 specification. parameter symbol conditions min typ max units supply voltage v cc (note 1) 2.7 5.5 v input logic 1 (sda, scl, a0, a1) v ih 0.7 x v cc v cc + 0.3 v input logic 0 (sda, scl, a0, a1) v il -0.3 0.3 x v cc v full-scale resistor values r fs0 , r fs1 , r fs2 , r fs3 (note 2) 40 160 k dc electrical characteristics (v cc = +2.7v to +5.5v, t a = -40? to +85?.) parameter symbol conditions min typ max units DS4422 250 supply current i cc v cc = 5.5v (note 3) ds4424 250 a input leakage (sda, scl) i il v cc = 5.5v 1 a output leakage (sda) i l 1 a v ol = 0.4v 3 output current low (sda) i ol v ol = 0.6v 6 ma rfs voltage v rfs 0.976 v i/o capacitance c i/o 10 pf output current source characteristics (v cc = +2.7v to +5.5v, t a = -40? to +85?.) parameter symbol conditions min typ max units output voltage for sinking current v out:sink (note 4) 0.5 3.5 v output voltage for sourcing current v out: source (note 4) 0 v cc - 0.75 v full-scale sink output current i out:sink (notes 1, 4) 50 200 a full-scale source output current i out:source (notes 1, 4) -200 -50 a output current full-scale accuracy i out:fs +25c, v cc = 3.3v; using 0.1% r fs resistor (note 2), v out0 = v out1 = 1.2v 6 % output current temperature coefficient i out:tc (note 5) 75 ppm/c
DS4422/ds4424 two-/four-channel, i 2 c, 7-bit sink/source current dac _______________________________________________________________________________________ 3 note 1: all voltages with respect to ground. currents entering the ic are specified positive, and currents exiting the ic are negative. note 2: input resistors (r fs ) must be between the speciifed values to ensure the device meets its accuracy and linearity specifications. note 3: supply current specified with all outputs set to zero current setting. a0 and a1 are connected to gnd. sda and scl are con- nected to v cc . excludes current through r fs resistors (i rfs ). total current including i rfs is i cc + (2 x i rfs ). note 4: the output-voltage range must be satisfied to ensure the device meets its accuracy and linearity specifications. note 5: temperature drift excludes drift caused by external resistor. note 6: differential linearity is defined as the difference between the expected incremental current increase with respect to position and the actual increase. the expected incremental increase is the full-scale range divided by 127. note 7: guaranteed by design. note 8: integral linearity is defined as the difference between the expected value as a function of the setting and the actual value. the expected value is a straight line between the zero and the full-scale values proportional to the setting. note 9: timing shown is for fast-mode (400khz) operation. this device is also backward compatible with i 2 c standard-mode timing. note 10: c b ?otal capacitance of one bus line in pf. output current source characteristics (continued) (v cc = +2.7v to +5.5v, t a = -40? to +85?.) parameter symbol conditions min typ max units dc source 0.32 output current variation due to power-supply change dc sink 0.42 %/v dc source, v out measure at 1.2v 0.16 output current variation due to output-voltage change dc sink, v out measure at 1.2v 0.16 %/v output leakage current at zero current setting i zero -1 +1 a output current differential linearity dnl (notes 6, 7) -0.5 +0.5 lsb output current integral linearity inl (notes 7, 8) -1 +1 lsb ac electrical characteristics (v cc = +2.7v to +5.5v, t a = -40? to +85?.) parameter symbol conditions min typ max units scl clock frequency f scl (note 9) 0 400 khz bus free time between stop and start conditions t buf 1.3 s hold time (repeated) start condition t hd:sta 0.6 s low period of scl t low 1.3 s high period of scl t high 0.6 s data hold time t dh:dat 0 0.9 s data setup time t su:dat 100 ns start setup time t su:sta 0.6 s sda and scl rise time t r (note 10) 20 + 0.1c b 300 ns sda and scl fall time t f (note 10) 20 + 0.1c b 300 ns stop setup time t su:sto 0.6 s sda and scl capacitive loading c b (note 10) 400 pf
DS4422/ds4424 two-/four-channel, i 2 c, 7-bit sink/source current dac 4 _______________________________________________________________________________________ typical operating characteristics (t a = +25?, unless otherwise noted.) supply current vs. supply voltage DS4422/4 toc01 supply voltage (v) supply current ( a) 5.0 4.5 4.0 3.5 3.0 50 100 150 200 250 0 2.5 5.5 does not include current drawn by resistors connected to fs0, fs1, fs2, or fs3 supply current vs. temperature DS4422/4 toc02 temperature ( c) supply current ( a) 80 60 40 20 0 -20 50 100 150 200 250 0 -40 v cc = 5.0v v cc = 2.7v v cc = 3.3v does not include current drawn by resistors connected to fs0, fs1, fs2, or fs3 voltco (source) DS4422/4 toc03 v out (v) i out ( a) 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 -225 -200 -175 -150 -250 0 5.0 40k load on fs0, fs1, fs2, and fs3 voltco (sink) DS4422/4 toc04 v out (v) i out ( a) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 175 200 225 250 150 0 4.0 40k load on fs0, fs1, fs2, and fs3 temperature coefficient vs. setting (source) DS4422/4 toc05 setting (dec) temperature coefficient ( c/ppm) 125 100 75 50 25 -50 0 50 100 150 200 -100 0 +25 c to -40 c +25 c to +85 c for the 50 a to 200 a current source range temperature coefficient vs. setting (sink) DS4422/4 toc06 setting (dec) temperature coefficient ( c/ppm) 125 100 75 50 25 -200 -150 -100 -50 0 50 -250 0 +25 c to -40 c +25 c to +85 c for the 50 a to 200 a current sink range integral linearity DS4422/4 toc07 setting (dec) inl (lsb) 125 100 25 50 75 -0.75 -0.50 -0.25 0 0.25 0.50 0.75 1.00 -1.00 0 for the 50 a to 200 a current source and sink range differential linearity DS4422/4 toc08 setting (dec) dnl (lsb) 125 100 75 50 25 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 for the 50 a to 200 a current source and sink range
DS4422/ds4424 two-/four-channel, i 2 c, 7-bit sink/source current dac _______________________________________________________________________________________ 5 v cc v cc r fs0 r fs1 r fs2 r fs3 sda scl a1 a0 gnd fs0 fs1 out1 out0 current dac0 f8h f9h source or sink mode fs2 out2 fs3 out3 current dac3 127 positions each for sink and source mode fah fbh current dac1 current dac2 i 2 c-compatible serial interface DS4422/ds4424 ds4424 only block diagram pin ds4424 DS4422 name function 1 1 sda i 2 c serial data. input/output for i 2 c data. 2 2 scl i 2 c serial clock. input for i 2 c clock. 3 3 gnd ground 4 fs3 5 fs2 6 6 fs1 7 7 fs0 full-scale calibration input. a resistor to ground on these pins determines the full-scale current for each output. fs0 controls out0, fs1 controls out1, etc. (the DS4422 has only two inputs: fs0 and fs1.) 8 8 out0 10 10 out1 12 out2 14 out3 current output. sinks or sources the current determined by the i 2 c interface and the resistance connected to fsx. (the DS4422 has only two outputs: out0 and out1.) 9, 11 9, 11 a0, a1 address select inputs. determines the i 2 c slave address by connecting v cc or gnd. see the detailed description section for the available device addresses. 13 13 v cc power supply 4, 5, 12, 14 n.c. no connection ep exposed pad. leave floating or connect to gnd. pin description
DS4422/ds4424 two-/four-channel, i 2 c, 7-bit sink/source current dac 6 _______________________________________________________________________________________ detailed description the DS4422/ds4424 contain two or four i 2 c adjustable current sources that are each capable of sinking and sourcing current. each output (out0, out1, out2, and out3) has 127 sink and 127 source settings that can be controlled by the i 2 c interface. the full-scale ranges and corresponding step sizes of the outputs are deter- mined by external resistors, connected to pins fs0, fs1, fs2, and fs3, that can adjust the output current over a 4:1 range. pins out2, out3, fs2, and fs3 are only available on the ds4424. the formula to determine r fs (connected to the fsx pins) to attain the desired full-scale current range is: equation 1: where i fs is the desired full-scale current value, v rfs is the r fs voltage (see the dc electrical characteristics table), and r fs is the external resistor value. to calculate the output current value (i out ) based on the corresponding dac value (see table 1 for corresponding memory addresses), use equation 2. equation 2: on power-up the DS4422/ds4424 output zero current. this is done to prevent them from sinking or sourcing an incorrect amount of current before the system host con- troller has had a chance to modify the device? setting. as a source for biasing instrumentation or other circuits, the DS4422/ds4424 provide a simple and inexpensive current source with an i 2 c interface for control. the adjustable full-scale range allows the application to get the most out of its 7-bit sink or source resolution. when used in adjustable power-supply applications (see typical operating circuit ), the DS4422/ds4424 do not affect the initial power-up voltage of the supply because they default to providing zero output current on power-up. as the devices source or sink current into the feedback-voltage node, they change the amount of out- put voltage required by the regulator to reach its steady- state operating point. using the external resistor, r fs , to set the output current range, the DS4422/ds4424 pro- vide some flexibility for adjusting the impedances of the feedback network or the range over which the power supply can be controlled or margined. i 2 c slave address the DS4422/ds4424 respond to one of four i 2 c slave addresses determined by the two address inputs, a0 and a1. the address inputs should be connected to either v cc or ground. table 1 lists the slave addresses determined by the address input combinations. memory organization to control the DS4422/ds4424? current sources, write to the memory addresses listed in table 2. the format of each output control register is given by: where: i d 1 i out fs = ac value dec () 27 r v 16 i fs rfs fs = 127 table 1. slave addresses a1 a0 slave address (hex) gnd gnd 20h gnd v cc 60h v cc gnd a0h v cc v cc e0h table 2. memory addresses memory address (hex) current source f8h out0 f9h out1 fah* out2* fbh* out3* *only for ds4424. msb lsb sd 6 d 5 d 4 d 3 d 2 d 1 d 0 bit name function power-on default s sign bit determines if dac sources or sinks current. for sink s = 0; for source s = 1. 0b d x data 7-bit data controlling dac output. setting 0000000b outputs zero current regardless of the state of the sign bit. 0000000b
DS4422/ds4424 two-/four-channel, i 2 c, 7-bit sink/source current dac _______________________________________________________________________________________ 7 example: r fs0 = 80k and register 0xf8h is written to a value of 0xaah. calculate the output current. i fs = (0.976v/80k ) x (127/16) = 96.838? the msb of the output register is 1, so the output is sourcing the value corresponding to position 2ah (42 decimal). the magnitude of the output current is equal to: 96.838? x (42/127) = 32.025? i 2 c serial interface description i 2 c definitions the following terminology is commonly used to describe i 2 c data transfers: i 2 c slave address: the slave address of the DS4422/ds4424 is determined by the state of the a0 and a1 pins (see table 1). master device: the master device controls the slave devices on the bus. the master device generates scl clock pulses and start and stop conditions. slave devices: slave devices send and receive data at the master? request. bus idle or not busy: time between stop and start conditions when both sda and scl are inactive and in their logic-high states. when the bus is idle it often initi- ates a low-power mode for slave devices. start condition: a start condition is generated by the master to initiate a new data transfer with a slave. transitioning sda from high to low while scl remains high generates a start condition. see figure 1 for applicable timing. stop condition: a stop condition is generated by the master to end a data transfer with a slave. transitioning sda from low to high while scl remains high generates a stop condition. see figure 1 for applicable timing. repeated start condition: the master can use a repeated start condition at the end of one data trans- fer to indicate that it will immediately initiate a new data transfer following the current one. repeated starts are commonly used during read operations to identify a spe- cific memory address to begin a data transfer. a repeat- ed start condition is issued identically to a normal start condition. see figure 1 for applicable timing. bit write: transitions of sda must occur during the low state of scl. the data on sda must remain valid and unchanged during the entire high pulse of scl, plus the setup and hold time requirements (figure 1). data is shifted into the device during the rising edge of the scl. bit read: at the end of a write operation, the master must release the sda bus line for the proper amount of setup time (figure 1) before the next rising edge of scl during a bit read. the device shifts out each bit of data on sda at the falling edge of the previous scl pulse and the data bit is valid at the rising edge of the current scl pulse. remember that the master generates all scl clock puls- es, including when it is reading bits from the slave. acknowledgement (ack and nack): an acknowledge- ment (ack) or not acknowledge (nack) is always the ninth bit transmitted during a byte transfer. the device receiving data (the master during a read or the slave during a write operation) performs an ack by transmit- ting a zero during the ninth bit. a device performs a figure 1. i 2 c timing diagram sda scl t hd:sta t low t high t r t f t buf t hd:dat t su:dat repeated start t su:sta t hd:sta t su:sto t sp stop note: timing is referenced to v il(max) and v ih(min) . start
DS4422/ds4424 two-/four-channel, i 2 c, 7-bit sink/source current dac 8 _______________________________________________________________________________________ nack by transmitting a one during the ninth bit. timing for the ack and nack is identical to all other bit writes (figure 2). an ack is the acknowledgment that the device is properly receiving data. a nack is used to terminate a read sequence or as an indication that the device is not receiving data. byte write: a byte write consists of 8 bits of information transferred from the master to the slave (most significant bit first) plus a 1-bit acknowledgement from the slave to the master. the 8 bits transmitted by the master are done according to the bit-write definition, and the acknowledgement is read using the bit-read definition. byte read: a byte read is an 8-bit information transfer from the slave to the master plus a 1-bit ack or nack from the master to the slave. the 8 bits of information that are transferred (most significant bit first) from the slave to the master are read by the master using the bit-read definition above, and the master transmits an ack using the bit write definition to receive additional data bytes. the master must nack the last byte read to terminated communication so the slave will return con- trol of sda to the master. slave address byte: each slave on the i 2 c bus responds to a slave address byte sent immediately fol- lowing a start condition. the slave address byte con- tains the slave address in the most significant 7 bits and the r/ w bit in the least significant bit. the DS4422/ds4424 slave address is determined by the state of the a0 and a1 address pins. table 1 describes the addresses corresponding to the state of a0 and a1. when the r/ w bit is 0 (such as in a0h), the master is indicating that it will write data to the slave. if r/ w = 1 (a1h in this case), the master is indicating that it wants to read from the slave. if an incorrect slave address is written, the DS4422/ds4424 assume the master is com- municating with another i 2 c device and ignore the communication until the next start condition is sent. memory address: during an i 2 c write operation, the master must transmit a memory address to identify the memory location where the slave is to store the data. the memory address is always the second byte trans- mitted during a write operation following the slave address byte. i 2 c communication writing to a slave: the master must generate a start condition, write the slave address byte (r/ w = 0), write the memory address, write the byte of data, and gener- ate a stop condition. remember that the master must read the slave? acknowledgement during all byte-write operations. reading from a slave: to read from the slave, the master generates a start condition, writes the slave address byte with r/ w = 1, reads the data byte with a nack to indicate the end of the transfer, and generates a stop condition. figure 2. i 2 c communication examples slave address* start start a1 a0 1 0 0 0 0 r/w slave ack slave ack slave ack msb lsb msb lsb msb lsb b7 b6 b5 b4 b3 b2 b1 b0 read/ write register/memory address b7 b6 b5 b4 b3 b2 b1 b0 data stop single byte write -write register f9h to 00h single byte read -read register f8h start repeated start 21h master nack stop 0 0100000 11111 000 f8h 00100 001 00100000 11111 001 20h f9h stop data example i 2 c transactions (when a0 and a1 are grounded) typical i 2 c write transaction *the slave address is determined by address pins a0 and a1. 00000 000 20h a) b) slave ack slave ack slave ack slave ack slave ack slave ack
DS4422/ds4424 two-/four-channel, i 2 c, 7-bit sink/source current dac _______________________________________________________________________________________ 9 applications information example calculations for an adjustable power supply in this example, the typical operating circuit is used as a base to create figure 3, a dc-dc output voltage of 2.0v with ?0% margin. the adjustable power sup- ply has a dc-dc converter output voltage, v out , of 2.0v and a dc-dc converter feedback voltage, v fb , of 0.8v. to determine the relationship of r 0a and r 0b , start with the equation: substituting v fb = 0.8v and v out = 2.0v, the relation- ship between r 0a and r 0b is determined to be: r 0a 1.5 x r 0b i out0 is chosen to be 100? (midrange source/sink current for the DS4422/ds4424). summing the currents into the feedback node produces the following: i out0 = i r0b - i r0a where: and: to create a 20% margin in the supply voltage, the value of v out is set to 2.4v. with these values in place, r 0b is calculated to be 2.67k , and r 0a is calculated to be 4.00k . the current dac in this configuration allows the output voltage to be moved linearly from 1.6v to 2.4v using 127 settings. this corresponds to a resolu- tion of 6.3mv/step. v cc decoupling to achieve the best results when using the DS4422/ ds4424, decouple the power supply with a 0.01? or 0.1? capacitor. use a high-quality ceramic surface- mount capacitor if possible. surface-mount compo- nents minimize lead inductance, which improves performance, and ceramic capacitors tend to have adequate high-frequency response for decoupling applications. i vv r r0a out fb 0a = ? i v r r0b fb 0b = v r rr fb 0b 0a + 0b out = v dc-dc converter fb out sda scl a0 a1 out0 gnd *v out and v fb values are determined by the dc-dc converter and should not be confused with v out and v rfs of the DS4422/ds4424. r fs0 = 80k 4.7k 4.7k v cc v cc v out * = 2.0v v fb * = 0.8v fs0 r 0b = 2.67k r 0a = 4.00k DS4422/ ds4424 i 0a i 0b i out0 figure 3. example application circuit
DS4422/ds4424 two-/four-channel, i 2 c, 7-bit sink/source current dac maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 10 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2008 maxim integrated products is a registered trademark of maxim integrated products, inc. package information for the latest package outline information, go to www.maxim-ic.com/packages . top view 2 4 5 13 11 10 v cc a1 out1 scl fs3 (n.c.) fs2 (n.c.) ( ) indicates DS4422 only. *exposed pad *ep 1 + 14 out3 (n.c.) out2 (n.c.) sda 3 12 gnd 6 9 a0 fs1 7 8 out0 fs0 DS4422/ ds4424 pin configuration package type package code document no. 14 tdfn t1433+2 21-0137
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